Special Section on Selected Papers from the 8th Karuizawa Workshop Estimation of Short-Circuit Power Dissipation for Static CMOS Gates
نویسنده
چکیده
We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing shortcircuit current by a piece-wise linear function and considering a current owing from input node to output node through gate capacitances, the accuracy is improved signi cantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools. key words: short-circuit power dissipation, short-circuit current, simulation of power dissipation, low power design, power estimation
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